An important aspect of the manufacture of integrated circuits (IC's) is the post-production testing process. The goal of the post-production testing process is to apply test inputs to a device and determine if the device is defective. Preferably, this defect detection process occurs as early point as possible since further integration of faulty components rapidly becomes very expensive. Consider for example, attempting to determine the location of a faulty IC in a personal computer system. There are several different kinds of tests that can be applied to IC defect testing. Exhaustive tests seek to apply every possible input in order to determine if any defects are present in the IC. Functional testing tests the functions present on the IC for correct operation. The fault model test determines each type of fault that is likely to occur, and devises tests for these common faults. The exhaustive test can be the most time-consuming and may also be expensive. Functional testing is problematic in that the test design must accurately ensure that all functionality is correctly tested. Functionality testing requires application specific knowledge to ensure that all incorporated functionality has been tested. Fault modeling will detect the faults assumed within the framework of the fault model. An example of the fault model is the stuck-at fault model. This model assumes a limited number of faults and assumes that the faults are permanent.
A well-designed test plan should use the least number of test inputs to cover the most number of defects or defective dice (DD's), and the test plan should be designed so that a test sequence is executed in an efficient fashion. Many of the exhaustive, functional, and fault models are based upon RTL and schematics. Thus the influence of the physical layout of the IC and the manufacture process (PLMP) on the defect creation in IC circuits is not exploited in the test strategy. The lack of relation between the test input data creation and the PLMP makes these methods susceptible to having redundant tests and performing a test inefficiently. The number of redundant tests and inefficient tests (RIT's) is a valuable parameter to consider when designing test plans, since there is a strong benefit in terms of reducing test execution time and test complexity when the number of RIT's are reduced. Current strategies that reduce the number of RIT's seek to eliminate the execution of redundant tests in the IC testing process using the same exhaustive, functional, and fault model strategies used in IC standardized IC testing.
Eliminating redundant tests and reordering tests to increase the test efficiency has become an important area of research as the IC test becomes increasingly expensive. In IC testing, tests are generated using simulations and other means. Evaluating the tests is important for increasing test efficiency and reducing test time. Efficient numerical algorithms for analyzing the test redundancy and the test sequence efficiency are required to meet the need for IC test time reduction techniques.
Thus, there is an unmet need in the art for an efficient numerical algorithm for analyzing a given test sequence redundancy and efficiency.